Three-dimensional (3D) wafer-to-wafer vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance. One major challenge of 3D interconnects on a single wafer or in a wafer-to-wafer vertical stack is through-via that provides a signal path for high impedance signals to traverse from one side of the wafer to the other. Through silicon via (TSV) is typically fabricated to provide the through-via filled with a conducting material that pass completely through the layer to contact and connect with the other TSVs and conductors of the bonded layers. Examples of methods forming TSVs after the first interconnect metallization process are described in U.S. Pat. No. 6,642,081 to Patti and U.S. Pat. No. 6,897,125 to Morrow, et al. One disadvantage is that the density of the via is typically less because of etch and design limitations, potentially creating connection, contact, and reliability problems. An additional limitation to current TSV systems and methods is the limited availability for thermal dissipation. Therefore, should there be a desire to design TSVs for thermal dissipation, those TSVs will typically occupy the area for normal design, since the contact and metallization layers are already in place. The article entitled: “Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs”, by Robert S. Patti, Proceedings of the IEEE, pp. 1214-1224, Vol. 94, No. 6, June. 2006, (incorporated herein by reference), presents examples of super-contact processes forming tungsten-filled TSVs before the contact process. The super-contact process may impact precision in photolithography and deposition during the subsequent contact process due to stress induced by the huge tungsten-filled TSV.